// Multiple-cycle channel
module mc_channel(clock, d_in, d_out, reset);
	parameter width = 16;
	parameter depth = 3;
	parameter depth_sz = 2;
	input clock;
	input reset;
	
	input [width-1:0] d_in;
	output wire [width-1:0] d_out;
	
	reg [depth_sz-1:0] counter;
		
	
	reg [width-1:0] q [depth-1:0];
	
	always @(posedge clock or negedge reset) begin
		if (!reset) begin
			for(counter=depth-1; counter>0; counter=counter-1) begin
				q[counter] <= 0;
			end
			q[0] <= 0;
		end
		else begin

			for(counter=depth-1; counter>0; counter=counter-1) begin
				q[counter] <= q[counter-1];
			end
			q[0] <= d_in;
		end

		
	end
	
	assign d_out = q[depth-1];
	

	
endmodule 
